3D Packaging & Heterogeneous Integration

Semiconductor technology is facing a new era in which device scaling is no longer sustainable in near future due to the physical limitations of devices. Therefore, the semiconductor industry is paying attention to system scaling, which is why advanced packaging technology has become very important. A key solution for system scaling in the field of semiconductor is heterogeneous integration (HI), which bridges the interconnect gap between transistors and packages, increases functionality, and improves cost/performance benefits. Heterogeneous Integration is the integration of separately manufactured components into system-in-package (SIP) using a variety of advanced packaging technologies such as 3D packaging, wafer level packaging, and chiplet technologies. Our lab is currently researching on the process and reliability of 3D Cu-Cu bonding and will continue to study the HI field for semiconductor system scaling.

Transparent Oxide Semiconductor

The electrical and optical properties of degenerate oxide semiconductor such as SnO2, In2O3and ZnO have been extensively studied. These materials have wide range of applications as transparent electrodes in electro-optic devices, protective coatings, gas sensors, heterojunction solar cells and transparent heat reflecting films. The high conductivity in these films can be created by donor doping or through control of intrinsic defects. Among many transparent oxides, our interest is on tin oxide thin film. The high conductivity in undoped but oxygen deficient SnO2is in general n-type. The goal of our research is to investigate highly conductive transparent p-type oxide semiconductor, to understand p-type characteristics and to fabricate a transparent device that can be applied to various electronic products for nano-micro electronics industries.

Thermal Management and Power Delivery

3D integrated circuit(IC) technology with TSV liquid cooling system is of interest. As a device scales down, both interconnect and packaging technologies are not fast enough to follow transistor’s technology. So an IC technology suffers from power delivery, thermal management, manufacturing yield, and so on. Especially for high density and high performance devices, power density increases significantly and it results in a major thermal problem and it becomes more severe for stacked ICs. Our lab is researching the liquid cooling system with TSV as one of device cooling methods for the next generation thermal management.

In the integrated circuit technologies, metal interconnection is more important than ever for a device performance. According to the International Technology Roadmap for Semiconductor, robust power delivery is one of scaling challenges due to increasing operating frequencies, increasing power density, and decreasing supply voltages. The on-chip power delivery problem becomes much harder as technology develops, and this is due to the combination of lower voltage, higher current density, thinner metal layer, and larger chip. The power delivery is in general controlled by minimizing IR drop and controlling circuit noise through circuit designs. Our solution to this problem is to develop advanced bump layers instead of circuit architectural changes.