International Patents
  • Packaged electroosmotic pumps using porous frits for cooling integrated circuits 7,274,106
  • Capacitor with insulating nanostructure 7,271,434
  • Capacitor with conducting nanostructure 7,265,406
  • Method and device for on-chip decoupling capacitor using nanostructures as bottom 7,244,983
  • Cooling micro-channels 7,227,257
  • Method and apparatus for low temperature copper to copper bonding 7,183,648
  • Self-aligned electrodes contained within the trenches of an electroosmotic pump fabricated in silicon or glass 7,105,382
  • Electroosmotic pumps using porous frits for cooling integrated circuit stacks 7,084,495
  • Methods of forming backside connections on a wafer stack 7,056,813
  • Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack 7,056,807
  • Wafer bonding using a flexible bladder press for three dimensional (3D) vertical stack integration 7,037,804
  • Microelectronic assembly having thermoelectric elements to cool a die and a method of making the same 7,034,394
  • Method and device for on-chip decoupling capacitor using nanostructures as bottom electrode 6,599,808
  • Etch stop layer for silicon (si) via etch in three-dimensional (3-d) wafer-to-wafer vertical stack 6,645,832
  • Barrier structure against corrosion and contamination in three-dimensional (3-d) wafer-to-wafer vertical stack 6,599,808
  • Process of vertically stacking multiple wafers supporting different active integrated circuit (ic) devices 6,762,076
  • Thinning techniques for wafer-to-wafer vertical stacks 6,790,748
  • Fabrication of 3-d capacitor with dual damascene process 6,790,780
  • Method and structure for interfacing electronic devices 6,870,270
  • Dielectric recess for wafer-to-wafer and die-to-die bonding and method of fabricating the same 6,887,769
  • Methods of processing thick ILD layers using spray coating or lamination for C4 wafer level thick metal integrated flow 6,943,440
  • Methods of forming backside connections on a wafer stack 6,897,125
  • Ultra-high capacitance device based on nanostructures 6,911,373
  • Etch thinning techniques for wafer-to-wafer vertical stacks 6,908,565
  • Differential Planarization 6,914,002
  • Using external radiators with electroosmotic pumps for cooling integrated circuits 6,992,381
  • Electro-osmotic pumps and micro-channels 6,981,849
  • Thick metal layer integrated process flow to improve power delivery and mechanical buffering 6,977,435
  • Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration and application 6,975,016
Korean Patents
  • 열계면층을 포함하는 반도체 소자 패키지 및 그 제조 방법 10-0046514
  • Low Temperature Cu Bonding method and Low Temperature Cu Bonding package 10-2099430
  • Cu Bonding method by 2 step plasma treatment and Cu Bonding package 10-2142387
  • Stacked cooling system for semiconductor device using ABL and TSV 10-0101228
  • Manufacturing method for wafer stack to protect wafer edge 10-0984848
  • Stack-type semiconductor package and manufacturing method 10-1080343
  • Manufacturing method for wafer stack 10-0936070
  • Methods of forming thin film solid oxide fuel cell 10-0724120
  • Semiconductor device package comprising thermal interface layer and method of fabricating of the same 10-2274190
  • Flip Chip Package 10-1326534